17. How to implement NIOS-designs

Please implement the designs of Chapter 1 (i.e. Verilog design) and Chapter 13 (i.e. NIOS design), before following this section.

Unlike Verilog designs, NIOS designs can not be run directly on a system just by downloading it. Therefore, only required design-files are provided (instead of complete project) for NIOS systems. We need to follow the steps provided in this section, to implement the NIOS design on the FPGA.

Note that Verilog codes and C/C++ codes of the tutorials are available on the website; these codes are provided inside the folders with name VerilogCodes (or Verilog) and CppCodes (or c, or software/ApplicationName_app) respectively. Along with these codes, .qsys files are also provided, which are used to generated the .sopc and .sopcinfo files. Lastly, pin assignments files for various Altera-boards are also provided in the zip folders.

Please follow the below step, to compile the NIOS design on new system. Further, if you change the location of the project in the computer (after compiling it successfully), then NIOS design must be implemented again by following the instruction in Section 17.4


Note that, this appendix uses the VHDL file, but same procedure is applicable for Verilog projects as well.

Codes files used in this section, are available in the folder ‘Appendix-How_to_implement_Nios_design’, which can be ‘downloaded from the website.

17.1. Create project

First create a new Quartus project (with any name) as shown in Section 1.2; and copy all the downloaded files (i.e. VerilogCodes, CppCodes, Pin-assignments and .qsys files) inside the main project directory.

17.2. Add all files from VerilogCodes folder

  • Next, add all the files inside the folder ‘VerilogCodes’, to project as shown in Fig. 17.1. Do not forget to select ‘All files’ option while adding the files as shown in Fig. 17.1.

Fig. 17.1 Add all files from VerilogCodes folder

  • In Chapter 1, we created ‘Verilog codes’ from the ‘Block schematic design’. These two designs are same, therefore while compilation the multiple-design error will be reported. Therefore we need to remove the duplicate designs as shown in Fig. 17.2. Note that, there are two duplicate designs i.e. one for half_adder and other is for full_adder as shown in the figure.

Fig. 17.2 Add all files from VerilogCodes folder

  • In this project, ‘full_adder_nios_test.bdf’ is the top-level design, which is shown in Fig. 17.3. Note that, here ‘name method’ is used to connect the ‘addr_input[2..0] with port ‘a’, ‘b’ and ‘c’. The method for giving name to a wire is shown in figure (see on the bottom-left side).

Fig. 17.3 Select this design i.e. ‘full_adder_nios_test.bdf’ as top level entity

  • Now, select ‘full_adder_nios_test.bdf’ as the top level entity, as shown in Fig. 17.4.

Fig. 17.4 Select top level entity

  • Modify the pin-assignment file and import it to the project . Also, make sure that correct FPGA-device is selected for the project. If problem in pin-assignments or device selection, then see Chapter 1 again.

17.3. Generate and Add QSys system

Open the Qsys from Tools–>Qsys; and then open the downloaded ‘.qsys’ file and follow the below steps,

  • First, refresh the system, by clicking on Files–>Refresh System.
  • Next, select the correct the device type as shown in Fig. 17.5.

Fig. 17.5 Change device family

  • Now, assign base addresses and interrupt numbers by clicking on System–>’Assign base addresses’ and ‘Assign interrupt numbers’.
  • If there are some errors after following the above steps, then delete and add the Nios-processor again; and make the necessary connection again i.e. clock and reset etc. Sometimes we may need to create the whole Qsys-design again, if error is not removed by following the above steps.
  • Finally, generate the system as shown in Fig. 17.6 ( or refer to Fig. 13.13 for generating system, if simulation is also used for NIOS design). Finally, close the Qsys after getting the message ‘Generate Completed’.

Fig. 17.6 Generate QSys system

  • Finally, add the Qsys design to main project. For this, we need to add the ‘.qip’ file generated by Qsys, which is available inside the synthesis folder. To add this file, follow the step in Fig. 17.1. You need to select the ‘All files’ option again to see the ‘.qip file’ as shown in Fig. 17.7.

Fig. 17.7 Change device family

  • Now, compile and load the design on FPGA system.

17.4. Nios system

Next, we need to create the NIOS system. For this, follow the below steps,

  • Follow the steps in Section 13.5 and ref{sec_add_modify_bsp` to create the NIOS-BSP file. Note that, you need to select the ‘.sopcinfo’ file, which is inside the current main-project-directory.
  • Next, we need to create the application file. To create the application, go to File–>New–>Nios II Application. Fill the application name e.g. ‘Application_fullAdder’ and select the BSP location as shown in Fig. 13.18.
  • Note that, if ‘c code’ is provided inside the ‘software folder (not in the ‘CppCodes’ or ‘c’ folders)’ e.g. ‘software/fullAdder_app’, then copy and paste folder-name as the application name i.e. ‘fullAdder_app’ to create the application file. Note that, we usually add ‘_app’ at the end of application name and ‘_bsp’ at the end of BSP name. In this case, ‘c code’ will automatically added to the project. Next, right click on the ‘c file’ and select ‘add to NIOS II build’; and skip the next step of adding ‘c file’, as it is already added in this case. Please see the video: Appendix - How to implement NIOS design, if you have problem in this part of tutorial.
  • Next, we need to import the ‘c’ code from folder ‘CppCodes (or c)’. For this, right click on the application and click on Import–>General–>File System–>From Directory; browse the directory, where we have saved the CppCodes and select the files as shown in Fig. 17.8. Finally, simulate the system as described in Section 13.8.

Fig. 17.8 Adding C files

  • Finally, simulate or load the design on FPGA. Please refer to Section 13.8 for simulation; and to Section 13.11 for loading the NIOS design on FPGA. Do not forget to keep reset button high, while loading the NIOS II design.
  • The current example will display the outputs on NIOS terminal, as shown in Fig. 17.9. Also, sum and carry values will be displayed on the LEDs.

Fig. 17.9 Nios Output of current design