16. Script execution in Quartus and Modelsim

To use the codes of the tutorial, Quartus and Modelsim softwares are discussed here. Please see the video: Create and simulate projects using Quartus and Modelsim, if you have problem in using Quartus or Modelsim software.

Note

Note that, this appendix uses the VHDL file, but same procedure is applicable for Verilog projects as well.

16.1. Quartus

In this section, ‘RTL view generation’ and ‘loading the design on FPGA board’ are discussed.

16.1.1. Generating the RTL view

The execute the codes, open the ‘overview.qpf’ using Quartus software. Then go to the files and right-click on the Verilog file to which you want to execute and click on ‘Set as Top-Level Entity’ as shown in Fig. 16.1. Then press ‘ctrl+L’ to start the compilation.

To generate the designs, go to Tools–>Netlist Viewer–>RTL Viewer; and it will display the design.

16.1.2. Loading design on FPGA board

Quartus software generates two types of files after compilation i.e. ‘.sof’ and ‘.pof’ file. These files are used to load the designs on the FPGA board. Note that ‘.sof’ file are erased once we turn off the FPGA device; whereas ‘.pof’ files are permanently loaded (unless removed or overwrite manually). For loading the design on the FPGA board, we need to make following two changes which are board specific,

  • First, we need to select the board by clicking on Assignments–>Device, and then select the correct board from the list.
  • Next, connect the input/output ports of the design to FPGA board by clicking on Assignments–>Pin Planner. It will show all the input and output ports of the design and we need to fill ‘location’ column for these ports.
  • To load the design on FPGA board, go to Tools–>Programmer.
  • Then select JTAG mode to load the ‘.sof’ file; or ‘Active Serial Programming’ mode for loading the ‘.pof’ file. Then click on ‘add file’ and select the ‘.sof/.pof’ file and click on ‘start’. In this way, the design will be loaded on FGPA board.
../_images/Quartus.jpg

Fig. 16.1 Quartus

16.2. Modelsim

We can also verify the results using modelsim. Follow the below steps for generating the waveforms,

  • First, open the modelsim and click on ‘compile’ button and select all (or desired) files; then press ‘Compile’ and ‘Done’ buttons. as shown in Fig. 16.2.

    ../_images/ModelsimSimulate.jpg

    Fig. 16.2 Modelsim: Compile and Simulate

  • Above step will show the compile files inside the ‘work library’ on the library panel; then right click the desired file (e.g. comparator2Bit.vhd) and press ‘simulate’, as shown on the left hand side of the Fig. 16.2. This will open a new window as shown in Fig. 16.3.

    ../_images/ModelsimWave.jpg

    Fig. 16.3 Modelsim: Waveforms

  • Right click the name of the entity (or desired signals for displaying) and click on ‘Add wave’, as shown in Fig. 16.3. This will show all the signals on the ‘wave default’ panel.

  • Now go to transcript window, and write following command there as shown in the bottom part of the Fig. 16.3. Note that these commands are applicable for 2-bit comparators only; for 1-bit comparator assign values of 1 bit i.e. ‘force a 1’ etc.

force a 00

force b 01

run

Above lines with assign the value 00 and 01 to inputs ‘a’ and ‘b’ respectively. ‘run’ command will run the code and since ‘a’ and ‘b’ are not equal in this case, therefore ‘eq’ will be set to zero and the waveforms will be displayed on ‘wave-default’ window, as shown in Fig. 16.3. Next, run following commands,

force a 01

run

Now ‘a’ and ‘b’ are equal therefore ‘eq’ will be set to 1 for this case. In this way we can verify the designs using Modelsim.