12. Interface

12.1. Introduction

The interface allows to create a group of signals, which can be used as ports in designs.

12.2. Define and use interface

  • In Listing 12.1, an interface is defined in Lines 3-9, which contains signals a, b, c and c_2 in it. Then, in module or_ex, these signals are used as shown in Lines 19-20 and 22. The simulation results are shown in Fig. 12.1.
Listing 12.1 Define and use interface
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// interface_ex.sv

interface logic_gate_if;

logic[3:0] a, b;
logic[5:0] c;
logic[5:0] c_2; // increment c by 2

endinterface


module or_ex(
    input logic[3:0] a, b,
    output logic[5:0] sum, sum_new
);

logic_gate_if lg ();  // import all signals from interface

assign lg.a = a;
assign lg.b = b;
assign sum = a+b;
assign sum_new = lg.a + lg.b + 2;  // increment sum by 2

endmodule
../_images/interface1.png

Fig. 12.1 Simulation results for Listing 12.1

  • Also, we can perform some assigments in the the interfaces as shown in Lines 9-10 of Listing 12.2. Also, these newly assigned values are assigned to output at Lines 23-24. The simulation results are same as in Fig. 12.1.

Warning

Do following, after making the changes in the code (otherwise changes will not be shown in the simulation),

  • Close the previous simulation
  • Then, right click on the ‘Run simulation->Reset Behaviour simulation’
  • Then, run the Behaviour-simulation again
Listing 12.2 Assigment in interface
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// interface_ex.sv

interface logic_gate_if;

logic[3:0] a, b;
logic[5:0] c;
logic[5:0] c_2; // increment c by 2

assign c = a + b;
assign c_2 = c + 2;
endinterface


module or_ex(
    input logic[3:0] a, b,
    output logic[5:0] sum, sum_2
);

logic_gate_if lg ();  // import all signals from interface

assign lg.a = a;
assign lg.b = b;
assign sum = lg.c;
assign sum_2 = lg.c_2; // increment sum by 2

endmodule