2. Overview

2.1. Introduction

Verilog is the hardware description language which is used to model the digital systems. In this tutorial, following 4 elements of Verilog designs are discussed briefly, which are used for modeling the digital system.

  • Design with Continuous assignment statements
  • Structural design
  • Design with Procedural assignment statements
  • Mixed design

The 2-bit comparators are implemented using various methods and corresponding designs are illustrated, to show the differences in these methods. Note that, all the features of Verilog can not be synthesized i.e. these features can not be converted into designs. Only, those features of Verilog are discussed in this tutorial, which can be synthesized.

2.2. Modeling styles

In Verilog, the model can be designed in four ways as shown in this section. Two bit comparator is designed with different styles; which generates the output ‘1’ if the numbers are equal, otherwise output is set to ‘0’.

2.2.1. Continuous assignment statements

In this modeling style, the relation between input and outputs are defined using signal assignments. ‘assign’ keyword is used for this purpose. In the other words, we do not define the structure of the design explicitly; we only define the relationships between the signals; and structure is implicitly created during synthesis process.

Explanation Listing 2.1:

Listing 2.1 is the example of ‘Continuous assignment statements’ design, where relationship between inputs and output are given in line 8. In verilog, ‘&’ sign is used for ‘and’ operation (line 8), and ‘//’ is used for comments (line 1). The ‘and gate (i.e. RTL view)’ generated by Listing 2.1 is shown in Fig. 2.1.

Note

To see the RTL view of the design, go to Tools–>Netlist Viewers–>RTL viewer

Note that, in lines 4 and 5, ‘wire’ keyword is used which is the ‘data type’. For continuous assignment statements ‘wire’ keyword is used; whereas ‘reg’ keyword is used for procedural assignment statement. Further, input ports can not be defined as ‘reg’. Note that, these keyword are not interchangeable and the differences between these ‘data types’ are discussed in Section 2.2.4. Further, more operators e.g. ‘and’, ‘not’ and ‘nand’ etc. are discussed in Chapter 3.

Listing 2.1 And gate
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// andEx.v

module andEx( 
    input wire x, y, 
    output wire z
);

assign z = x & y; // x and y
endmodule
../_images/andEx.jpg

Fig. 2.1 And gate, Listing 2.1

  • Listing 2.1 can be written as Listing 2.2, where module-definition contains name of ports only (Line 3); and types of ports are defined outside the module (Lines 5-6).

    Listing 2.2 And gate
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    // andEx2.v
    
    module andEx2(x, y, z);
    
    input wire x, y;
    output wire z;
    
    assign z = x & y;
    
    endmodule 
    

2.2.2. Comparators using Continuous assignment statements

In this section, two more examples of Continuous assignment statements are shown i.e. ‘1 bit’ and ‘2 bit’ comparators; which are used to demonstrate the differences between various modeling styles in the tutorial. Fig. 2.2 and Fig. 2.3 show the truth tables of ‘1 bit’ and ‘2 bit’ comparators. As the name suggests, the comparator compare the two values and sets the output ‘eq’ to 1, when both the input values are equal; otherwise ‘eq’ is set to zero. The corresponding boolean expressions are shown below,

For 1 bit comparator:

(2.1)\[eq = x' y' + x y\]

For 2 bit comparator:

(2.2)\[eq = a'[1]a'[0]b'[1]b'[0] + a'[1]a[0]b'[1]b[0] + a[1]a'[0]b[1]b'[0] + a[1]a[0]b[1]b[0]\]
../_images/TableComparator1Bit.jpg

Fig. 2.2 1 bit comparator, Listing 2.3

../_images/TableComparator2Bit.jpg

Fig. 2.3 2 bit comparator, Listing 2.4

Above two expressions are implemented using verilog in Listing 2.3 and Listing 2.4, which are explained below.

Explanation Listing 2.3:

Listing 2.3 implements the 1 bit comparator based on (2.1). Two intermediate signals are defined in Line 8. These two signals (s0 and s1) are defined to store the values of x’y’ and xy respectively. Values to these signals are assigned at Lines 10 and 11. In verilog, ‘not’ and ‘or’ operations are implemented using ‘~’ and ‘|’ signs as shown in Line 10 and 12 respectively. Finally (2.1) performs ‘or’ operation on these two signals, which is done at Line 12. When we compile this code using ‘Quartus software’, it implements the code into hardware design as shown in Fig. 2.4.

The compilation process to generate the design is shown in Appendix 17. Also, we can check the input-output relationships of this design using Modelsim, which is also discussed briefly in Appendix 17.

Listing 2.3 Comparator 1 Bit
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// comparator1Bit.v

module comparator1Bit(
    input wire x, y,
    output wire eq
);

wire s0, s1;

assign s0 = ~x & ~y;
assign s1 = x & y;
assign eq = s0 | s1;

endmodule

Note

Note that, the statements in ‘Continuous assignment statements’ and ‘structural modeling’ (described in Section 2.2.3) are the concurrent statements, i.e. these statements execute in parallel. In the other words, order of statements do not affect the behavior of the circuit; e.g. if we exchange the Lines 10, 11 and 12 in Listing 2.3, again we will get the Fig. 2.4 as implementation.

On the other hand, statements in ‘Procedural assignment statements’ (described in Section 2.2.4) executes sequentially and any changes in the order of statements will change the behavior of circuit.

Explanation :numref: Fig. 2.4

Fig. 2.4 is generated by Quartus software according to the verilog code shown in Listing 2.3. Here, s0 is the ‘and’ gate with inverted inputs x and y, which are generated according to Line 10 in Listing 2.3. Similarly, s1 ‘and’ gate is generated according to Line 11. Finally output of these two gates are applied to ‘or’ gate (named as ‘eq’) which is defined at Line 12 of the Listing 2.3.

../_images/comparator1Bit.JPG

Fig. 2.4 1 bit comparator, Listing 2.3

Explanation Listing 2.4

This listing implements the equation (2.2). Here, we are using two bit input, therefore ‘wire[1:0]’ is used at line 4. ‘1:0’ sets the 1 as MSB (most significant bit) and 0 as LSB(least significant bit) i.e. the a[1] and b[1] are the MSB, whereas a[0] and b[0] are the LSB. Since we need to store four signals (lines 10-13), therefore ‘s’ is defined as 4-bit vector in line 8. Rest of the working is same as Listing 2.3. The implementation of this listing is shown in Fig. 2.5.

Listing 2.4 Comparator 2 Bit
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// comparator2Bit.v

module comparator2Bit(
    input wire[1:0] a, b,
    output wire eq
);

wire[3:0] s;

assign s[0] = ~a[1] & ~a[0] & ~b[1] & ~b[0];
assign s[1] = ~a[1] &  a[0] & ~b[1] &  b[0];
assign s[2] =  a[1] & ~a[0] &  b[1] & ~b[0];
assign s[3] =  a[1] &  a[0] &  b[1] &  b[0];

assign eq = s[0] | s[1] | s[2] | s[3];
endmodule
../_images/comparator2Bit.JPG

Fig. 2.5 2 bit comparator, Listing 2.4

2.2.3. Structural modeling

In previous section, we designed the 2 bit comparator based on equation (2.2) . Further, we can design the 2 bit comparator using 1-bit comparator as well, with following steps,

  • First compare each bit of 2-bit numbers using 1-bit comparator; i.e. compare a[0] with b[0] and a[1] with b[1] using 1-bit comparator (as shown in Fig. 2.3).
  • If both the values are equal, then set the output ‘eq’ as 1, otherwise set it to zero.

This method is known as ‘structural’ modeling, where we use the pre-defined designs to create the new designs (instead of implementing the ‘boolean’ expression). This method is quite useful, because most of the large-systems are made up of various small design units. Also, it is easy to create, simulate and check the various small units instead of one large-system. Listing 2.5 is the example of structural designs, where 1-bit comparator is used to created a 2-bit comparator.

Explanation Listing 2.5

In this listing, Lines 4-5 define the two input ports of 2-bit size and one 1-bit output port. Then two signals are defined (Line 8) to store the outputs of two 1-bit comparators, as discussed below.

‘eq_bit0’ and ‘eq_bit1’ in Lines 10 and 11 are the names of the two 1-bit comparator, which are used in this design. We can see these names in the resulted design, which is shown in Listing 2.5.

Next, ‘comparator1Bit’ in Lines 10 and 11 is the name of the 1-bit comparator (defined in Listing 2.3). With this declaration, i.e. comparator1bit, we are calling the design of 1-bit comparator to current design.

Then, mapping statements e.g. .x(a[0]) in Lines 10 and 11, are assigning the values to the input and output port of 1-bit comparator. For example, in Line 10, input ports of 1-bit comparator i.e. x and y, are assigned the values of a[0] and b[0] respectively from this design; and the output y of 1-bit comparator is stored in the signal s0. Further, in Line 13, if signals s0 and s1 are 1 then ‘eq’ is set to 1 using ‘and’ gate, otherwise it will be set to 0. Final design generated by Quartus software for Listing 2.5 is shown in Fig. 2.6.

Listing 2.5 Structure modeling using work directory
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// comparator2BitStruct.v

module comparator2BitStruct(
    input wire[1:0] a, b,
    output wire eq
);

wire s0, s1;

comparator1Bit eq_bit0 (.x(a[0]), .y(b[0]), .eq(s0));
comparator1Bit eq_bit1 (.x(a[1]), .y(b[1]), .eq(s1));

assign eq = s0 & s1;
endmodule
../_images/comparator2BitStruct.JPG

Fig. 2.6 2 bit comparator, Listing 2.5

Explanation Fig. 2.6

In this figure, a[1..0] and b[1..0] are the input bits whereas ‘eq’ is the output bit. Thick Lines after a[1..0] and b[1..0] show that there are more than 1 bits e.g. in this case these Lines have two bits. These thick Lines are changed to thin Lines before going to comparators; which indicates that only 1 bit is sent as input to comparator.

In ‘comparator1Bit: eq_bit0’, ‘comparator1Bit’ is the name of the module defined for 1-bit comparator (Listing 2.3); whereas the ‘eq_bit0’ is the name of this module defined in Line 10 of listing Listing 2.5. Lastly outputs of two 1-bit comparator are sent to ‘and’ gate according to Line 13 in listing Listing 2.5.

Hence, from this figure we can see that the 2-bit comparator can be designed by using two 1-bit comparator.

2.2.4. Procedural assignment statements

In Procedural assignment statements, the ‘always’ keyword is used and all the statements inside the always statement execute sequentially. Various conditional and loop statements can be used inside the process block as shown in Listing 2.6. Further, always blocks are concurrent blocks, i.e. if the design has multiple always blocks (see Listing 2.7), then all the always blocks will execute in parallel.

Explanation Listing 2.6:

The ‘always’ block is declared in Line 8, which begins and ends at Line 9 and 14 respectively. Therefore all the statements between Line 9 to 14 will execute sequentially and Quartus Software will generate the design based on the sequences of the statements. Any changes in the sequences will result in different design.

Note that, the output port ‘eq’ is declared as reg at Line 5. If we assign value to the signal inside the ‘always’ block then that signal must be declared as ‘reg’ e.g. value of ‘eq’ is assigned in Line 11 and 13, which are inside the ‘always’ block; hence ‘eq’ is declared as reg.

The ‘always’ keyword takes two arguments in Line 8 (known as ‘sensitivity list’), which indicates that the process block will be executed if and only if there are some changes in ‘a’ and ‘b’. ‘@’ is used after ‘always’ for defining the sensitivity list. In Line 10-13, the ‘if’ statement is declared which sets the value of ‘eq’ to 1 if both the bits are equal (Line 10-11), otherwise ‘eq’ will be set to 0 (Line 12-13). Fig. 2.7 shows the design generated by the Quartus Software for this listing. ‘==’ in Line 10 is one of the condition operators; whereas && is the logical operator, which are discussed in detail in Chapter 3.

Listing 2.6 Procedural assignment statement
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// comparator2BitProcedure.v

module comparator2BitProcedure(
    input wire[1:0] a, b,
    output reg eq
);

always @(a,b)
begin
    if (a[0]==b[0] && a[1]==b[1]) 
        eq = 1;
    else
        eq = 0;
end
endmodule
../_images/comparator2BitProcedure.jpg

Fig. 2.7 2 bit comparator, Listing 2.6

2.2.5. Mixed modeling

We can mixed all the modeling styles together as shown in Listing 2.7. Here two always blocks are used in Line 10 and 18, which is the ‘procedural assignment statements’. Then in Line 26, ‘continuous assignment statement’ is used for assigning the value to output variable ‘eq’.

Explanation Listing 2.7

Note that, output ‘eq’ is defined as ‘wire’ (as value to ‘eq’ is assigned using continuous assignment statement), whereas signals ‘s0’ and ‘s1’ is defined as ‘reg’ (as values are assigned using procedural assignment statement i.e. inside the ‘always’ block). Two always blocks are used here. Always block at Line 10 checks whether the LSB of two numbers are equal or not; if equal then signal ‘s0’ is set to 1 otherwise it is set to 0. Similarly, the always block at Line 18, sets the value of ‘s1’ based on MSB values. Lastly, Line 16 sets the output ‘eq’ to 1 if both ‘s0’ and ‘s1’ are 1, otherwise it is set to 0. The design generated for this listing is shown in Fig. 2.8.

Listing 2.7 Multiple procedural assignment statements
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// comparator2BitMixed.v

module comparator2BitMixed(
    input wire[1:0] a, b,
    output wire eq
);

reg[1:0] s0, s1;

always @(a,b)
begin
    if (a[0]==b[0]) 
        s0 = 1;
    else
        s0 = 0;
end

always @(a,b)
begin
    if (a[1]==b[1]) 
        s1 = 1;
    else
        s1 = 0;
end

assign eq = s0 & s1;
endmodule
../_images/comparator2BitMixed.jpg

Fig. 2.8 2 bit comparator, Listing 2.7

2.3. Conclusion

In this tutorial, various features of Verilog designs are discussed briefly. We designed the two bit comparator with four modeling styles i.e. Continuous assignment statement, Structural design, Procedural assignment statement and Mixed styles. Also, differences between the generated-designs with these four methods are shown.