15. UART, SDRAM and Python

15.1. Introduction

In this chapter, UART communication is discussed for NIOS design. Values of Sin(x) is generated using NIOS and the data is received by computer using UART cable. Since, onchip memory is smaller for storing these values, therefore external memory i.e. SDRAM is used. Further, the received data is stored in a file using ‘Tera Term’ software; finally live-plotting of data is performed using Python.

In this chapter, we will learn following topics,

  • UART interface,
  • Receiving the data on computer using UART communication,
  • SDRAM interface,
  • Saving data generated by NIOS desgin to a file using ‘Tera Term’,
  • Updating a existing QSys design and corresponding Verilog and NIOS design,
  • Live-plotting of data using Python.

15.2. UART interface

First, create a empty project with name ‘UartComm’ (see Section 1.2). Next, open the QSys from Tools–>Qsys. Add ‘Nios Processor’, ‘On-chip RAM (with 20k total-memory-size), ‘JTAG UART’ and ‘UART (RS-232 Serial Port)’ (all with default settings). Note that, Baud rate for UART is set to ‘115200’ (see Fig. 15.1), which will be used while getting the data on computer. Lastly, connect these items as shown in Fig. 15.2; save it as ‘Uart_Qsys.qsys’ and finally generate the Qsys system and close the Qsys. Please see Section 13.4, if you have problem in generating the QSys system.

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Fig. 15.1 UART settings

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Fig. 15.2 Qsys connections

Now, add the file ‘Uart_Qsys.qip’ to the Verilog project. Next, create a new ‘Block diagram (.bdf) file and import the Qsys design to it and assign correct pin numbers to it, as shown in Fig. 15.3. Save it as ‘Uart_top.bdf’ and set it as ‘top level entity’. Lastly, import the pin assignment file and compile the design. Finally, load the design on FPGA board.

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Fig. 15.3 Top level entity ‘Uart_top.bdf’

15.3. NIOS design

In Chapter 13, we created the ‘BSP’ and ‘application’ file separately for NIOS design. In this chapter, we will use the template provided with NIOS to create the design. For this, open the NIOS software and go to ‘Files–>New–>NIOS II Application and BSP from Template’. Next, Select the ‘UART_Qsys.sopcinfo’ file and ‘Hello World’ template and provide the desired name to project e.g. UART_comm_app, as shown in Fig , and click ‘next’. In this window, enter the desired name for BSP file in the ‘Project name’ column e.g. ‘UART_comm_bsp’; and click on Finish.

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Fig. 15.4 Create NIOS project from template

15.4. Communication through UART

To received the data on computer, we need some software like Putty or Tera Term. In this tutorial, we are using ‘Tera Term software, which can be downloaded freely. Also, we need to change the UART communication settings; so that, we can get messages through UART interface (instead of JTAG-UART) as shown next.

Right click on ‘UART_comm_bsp’ and go to ‘NIOS II–>BSP editor’; and select UART_115200 for various communication as shown in Fig. 15.5; and finally click on generate and then click on exit. Now, all the ‘printf’ statements will be send to computer via UART port (instead of Jtag-uart). We can change it to JTAG-UART again, by changing UART_115200 to JTAG-UART again. Note that, when we modify the BSP using BSP-editor, then we need to generate the system again.

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Fig. 15.5 UART communication settings in NIOS

Now, open the Tera Term and select the ‘Serial’ as shown in Fig. 15.6. Then go to ‘Setup–>Serial Port…’ and select the correct baud rate i.e. 115200 and click OK, as shown in Fig. 15.7.

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Fig. 15.6 Serial communication in Tera Term

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Fig. 15.7 Select correct baud rate

Finally, right click on ‘UART_comm_app’ in NIOS and go to ‘Run As–>3 NIOS 2 Hardware’. Now, we can see the output on the Tera Term terminal, as shown in Fig. 15.8.

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Fig. 15.8 ‘Hello from NIOS II!’ on Tera Term

15.5. SDRAM Interface

Our next aim is to generate the Sine waves using NIOS and then plot the waveforms using python. If we write the C-code in current design, then our system will report the memory issue as onchip memory is too small; therefore we need to use external memory. In this section, first, we will update the Qsys design with SDRAM interface, then we will update the Quartus design and finally add the C-code to generate the Sine waves.

15.5.1. Modify QSys

First, Open the UART_Qsys.qsys file in QSys software. Now, add SDRAM controller with default settings, as shown in Fig. 15.9. Next, connect all the ports of SDRMA as shown in Fig. 15.10. Then, double click the ‘nios2_qsys_0’ and select ‘SDRAM’ as reset and exception vector memory, as shown in Fig. 15.11.

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Fig. 15.9 SDRAM controller

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Fig. 15.10 SDRAM connections

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Fig. 15.11 Select SDRAM as vector memories

Next, we will add ‘Switches’ to control the amplitude of the sine waves. For this add the PIO device of ‘8 bit with type input’, and rename it as ‘switch’, as shown in Fig. 15.12 . Finally, go to System–>Assign base addresses, and generate the system.

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Fig. 15.12 Add switches for controlling the amplitude of sine waves

15.5.2. Modify Top level Quartus design

Now, open the ‘Uart_top.bdf’ file in Quartus. Right click on the ‘Uart_Qsys’ block and select ‘Update symbol or block’; then select the option ‘Selected symbol(s) or block(s)’ and press OK. It will display all the ports for ‘SDRAM’ and switches. Next, we need to assign the correct ‘pin names’ to these ports, as shown in Fig. 15.13.

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Fig. 15.13 Assigning Pins to SDRAM and Switches

Note that, there should be ‘-3 ns clock delay’ for SDRAM as compare to FPGA clock, therefore we need to add the clock with ‘-3 ns delay’. For this, double click on the Uart_top.bdf (anywhere in the file), and select ‘MegaWizard Plug-In Manager’. Then select ‘Create a new custom megafunction variation’ in the popped-up window and click next. Now, select ALTPLL from IO in Installed Plug-Ins option, as shown in Fig. 15.14, and click next. Then, follow the figures from Fig. 15.15 to Fig. 15.20 to add the ALTPLL to current design i.e. ‘Uart_top.bdf’. Finally, connect the ports of this design as shown in Fig. 15.21. Note that, in these connections, output of ATLPLL design is connected to ‘DRAM_CLK’, which is clock-port for DRAM. Lastly, compile and load the design on FPGA board.

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Fig. 15.14 ALTPLL generation

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Fig. 15.15 ALTPLL creation, step 1

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Fig. 15.16 ALTPLL creation, step 2

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Fig. 15.17 ALTPLL creation, step 3

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Fig. 15.18 ALTPLL creation, step 4

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Fig. 15.19 ALTPLL creation, step 5

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Fig. 15.20 ALTPLL creation, step 6

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Fig. 15.21 Connect ALTPLL design with existing design

15.5.3. Updating NIOS design

Since, we have udpated the QSys design, therefore the corresponding .sopcinfo file is also updated. Further, BSP files depends on the .sopcinfo file, therefore we need to update the BSP as well. For this, right click on ‘Uart_comm_bsp’ and go to ‘NIOS II–>BSP Editor; and update the BSP as shown in Fig. 15.22 and click on ‘generate’ and then click ‘exit’. Note that, ‘enable’ options are unchecked now, because we are using External memory, which is quite bigger than onchip-memory, so we do not need ‘small’ size options.

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Fig. 15.22 Update BSP for new Qsys design

Now, update the ‘hello_world.c’ file as shown in Listing 15.1.

Listing 15.1 Sin and Cos wave generation
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//hello_world.c
#include "io.h"
#include "alt_types.h"
#include "system.h"
#include "math.h"

int main(){

    float i=0, sin_value, cos_value;
    alt_u8 amplitude;

    while(1){
        amplitude = IORD(SWITCH_BASE, 0);

        sin_value =  (int)amplitude * (float)sin(i);
        cos_value =  (int)amplitude * (float)cos(i);

        printf("%f,%f\n", sin_value, cos_value);
        i = i+0.01;

  }
}

In Tera Term, we can save the received values in text file as well. Next, go Files–>Log and select the filename at desired location to save the data e.g. ‘sineData.txt’.

Finally, right click on ‘UART_comm_app’ in NIOS and go to ‘Run As–>3 NIOS 2 Hardware’. Now, we can see the decimal values on the screen. If all the switches are at ‘0’ position, then values will be ‘0.000’ as amplitude is zero. Further, we can use any combination of 8 Switches to increase the amplitude of the sine and cosine waves. Also, result will be stored in the ‘sineData.txt’ file. Content of this file is shown in Fig. 15.23

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Fig. 15.23 Content of ‘sineData.txt’ file

15.6. Live plotting the data

In the previous section, we store the sine and cosine wave data on the ‘sineData.txt’ using UART communication. Now, our last task is to plot this data continuously, so that it look line animation. For this save the Listing 15.2, in the location where ‘sineData.txt’ is saved. Now, open the command prompt and go to the location of python file. Finally, type ‘python main.py’ and press enter. This will start plotting the waveform continuously based on the data received and stored on the ‘sineData.txt’ file. The corresponding plots are shown in Fig. 15.24.

Listing 15.2 Code for live plotting of logged data
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import matplotlib.pyplot as plt
import matplotlib.animation as animation

fig = plt.figure()
ax1 = fig.add_subplot(2,1,1)
ax2 = fig.add_subplot(2,1,2)

def animate(i):
    readData = open("sineData.txt","r").read()
    data = readData.split('\n')
    sin_array = []
    cos_array = []
    for d in data:
        if len(d)>1:
            sin, cos = d.split(',')
            sin_array.append(sin)
            cos_array.append(cos)
    ax1.clear()
    ax1.plot(sin_array)

    ax2.clear()
    ax2.plot(cos_array)

def main():
    ani = animation.FuncAnimation(fig, animate)
    plt.show()

if __name__ == '__main__':
    main()
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Fig. 15.24 Plot of ‘sineData.txt’ file

15.7. Conclusion

In this chapter, first we display the ‘Hello’ message using UART and Tera Term. Then, SDRAM is included in the design and correspondingly all the other designs are updated i.e. Quartus and NIOS. Then, the data is stored in the text file and finally it is plotted with the help of Python programming language.