5. VHDL designs in Verilog

5.1. Introduction

Since, both VHDL and Verilog are widely used in FPGA designs, therefore it be beneficial to combine both the designs together; rather than transforming the Verilog code to VHDL and vice versa. This chapter presents the use of VHDL design in the Verilog codes.

5.2. VHDL designs in Verilog

For using VHDL in verilog designs, only proper component instantiation is required as shown in this section. Design of 1 bit comparator in Listing 5.1 (which is written using VHDL) is same as the design of Listing 2.3. Design generated by Listing 5.1 is shown in Fig. 5.1.

Listing 5.1 1 bit comparator in Verilog
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--comparator1BitVHDL.vhd

library ieee; 
use ieee.std_logic_1164.all;

entity comparator1BitVHDL is
  port(
    x, y : in std_logic;
    eq : out std_logic
  ); 
end comparator1BitVHDL;

architecture dataflow1Bit of comparator1BitVHDL is
  signal s0, s1: std_logic; 
begin
  s0 <= (not x) and (not y);
  s1 <= x and y;
  
  eq <= s0 or s1;
end dataflow1Bit;  
../_images/comparator1BitVHDL.jpg

Fig. 5.1 1 bit comparator using VHDL

Explanation Listing 5.2

This listing is exactly same as Listing 2.5. To design the 2 bit comparator, two 1 bit comparators are instantiated in line 10 and 11. The final design generated for the two bit comparator is shown Fig. 5.2. In this way, we can use the VHDL designs in Verilog codes.

Listing 5.2 VHDL design in Verilog
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// comparator2BitWithVHDL.v
module comparator2BitWithVHDL(
    input wire[1:0] a, b,
    output wire eq
);

wire s0, s1;

// instantiate 1 bit comparator
comparator1BitVHDL eq_bit0 (.x(a[0]), .y(b[0]), .eq(s0));
comparator1BitVHDL eq_bit1 (.x(a[1]), .y(b[1]), .eq(s1));

assign eq = s0 & s1;
endmodule
../_images/comparator2BitWithVHDL.jpg

Fig. 5.2 2 bit comparator using VHDL and Verilog

5.3. Conclusion

In this chapter, VHDL files are used in Verilog designs. From the examples shown in this chapter, it is clear that we need not to do anything special to using VHDL files in Verilog designs; only proper port mapping i.e. component instantiation is required.