# 6. Visual verifications of designs¶

## 6.1. Introduction¶

In previous chapters, we saw various elements of Verilog language with some design examples, which were verified using simulations. In this chapter, various smaller units are designed and then combined together to make the large systems. Further, visual verification is performed in this chapter i.e. the designs are verified using LED displays. Finally, in Section 6.6, output of mod-m is displayed on various LEDs using smaller designs i.e. counters, clock-ticks and seven segment displays.

## 6.2. Flip flops¶

Flip flops are the sequential circuits which are used to store 1-bit. In this section, D flip flop is designed with various functionalities in it.

### 6.2.1. D flip flop¶

In Listing 6.1, the basic D flip flop is designed with reset button. Output of the flip flop is set to zero if reset value is ‘1’, otherwise output has the same value as input. Further, change in the output value occurs during ‘positive edge’ of the clock. Design generated by Listing 6.1 is shown in Fig. 6.1.

Explanation Listing 6.1

In the listing, ‘d’ and ‘q’ are the input and output respectively of the D flip flop. In Line 12, output of the D flip flop is set to zero when reset is ‘1’. In Line 9, ‘posedge’ is used for checking the ‘rising edge’ of the clock in Verilog i.e. all the statements inside the ‘always’ block will be executed during rising edge of the clock. Next in Line 14, input value is sent to the output during the rising edge of the clock.

Listing 6.1 Basic D flip flop
  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // BasicDFF.v module BasicDFF( input wire clk, reset, input wire d, output reg q ); always @(posedge clk, posedge reset) begin if (reset == 1) q = 0; else q = d; end endmodule 

Fig. 6.1 Basic D flip flop, Listing 6.1

### 6.2.2. D flip flop with Enable port¶

Note that, in Fig. 6.1, the enable button i.e. ‘ENA’ is still not connected. Enable button can be used for allowing the change in the output at desired time instant; e.g. if we want to change the output of the D flip flop on every $$10^{th}$$ clock, then we can set the enable to ‘1’ for every $$10^{th}$$ clock and ‘0’ for rest of the clocks. We call this as ‘tick’ at every 10 clock cycle; and we will see various examples of ‘ticks’ in this chapter. In this way, we can control the output of the D flip flop. To add the enable functionality in the flip flop, ‘en == 1’ is added in Line 14 of Listing 6.2. The design generated by the listing is shown in Fig. 6.2

Listing 6.2 D flip flop with enable
  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 // D_FF.v module D_FF( input wire clk, reset, en, //en: enable input wire d, output reg q ); // check for positive edge of clock and reset always @(posedge clk, posedge reset) begin if (reset == 1) q <= 0; else if (en == 1) q <= d; end endmodule 

Fig. 6.2 D flip flop with enable, Listing 6.2

## 6.3. Counters¶

In this section, two types of counters are designed i.e. binary counter and mod-m counter.

### 6.3.1. Binary counter¶

In Listing 6.3, N-bit binary counter is designed which counts the number from 0 to $$2^N-1$$. After reaching to maximum count i.e. $$2^N-1$$, it again starts the count from 0.

Explanation Listing 6.3

In the listing, two output ports are defined i.e. ‘count’ and ‘complete_tick’, where ‘complete_tick’ is used to generate tick when the ‘count’ reached to it’s maximum value. In Line 13, ‘MAX_COUNT’ is used to define the maximum count for ‘N’ bit counter; where ‘N’ is defined as parameter in Line 5.

Signal ‘count_reg’ is defined in Line 15 and assigned to output at Line 31. Value of ‘count_reg’ is increased by one and assigned to ‘count_next’ in Line 26. Then in next clock cycle, this increased value of ‘count_reg’ (which is store in ‘count_next’) is assigned to ‘count_reg’ again through Line 23. Design generated by the listing is shown in Fig. 6.3.

Listing 6.3 N-bit binary counter
  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 // binaryCounter.v module binaryCounter #( parameter N = 3 //N bit binary counter ) ( input wire clk, reset, output wire complete_tick, output wire[N-1:0] count ); localparam MAX_COUNT = 2**N-1; // maximum value for N-bit reg[N-1:0] count_reg; wire[N-1:0] count_next; always @(posedge clk, posedge reset) begin if (reset == 1) count_reg <= 0; // set count to 0 if reset else count_reg <= count_next; // assign next value of count end assign count_next = count_reg + 1; // increase the count // generate tick on each maximum count assign complete_tick = (count_reg == MAX_COUNT) ? 1 : 0; assign count = count_reg; // assign value to output port endmodule 

Fig. 6.3 N-bit binary counter, Listing 6.3

Explanation Listing 6.3

In the figure, component ‘Equal0’ is generated according to Line 29. 32’h00…07 shows that counter is designed with maximum value 7. Output of ‘Equal0’ i.e. complete_tick is set to 1 whenever output is equal to maximum value i.e. 7.

‘count_reg[2:0]’ shows that three D flip flops are used to create the 3 bit register. Also, we used only ‘clk’ and ‘reset’ ports in the design therefore enable port i.e. ‘ENA’ is unconnected. ‘Add0’ is included in the design to increase the value of count according to Line 26. Finally, this increased value is assigned to output port in next clock cycle according to Line 23. The simulation waveforms for this design is shown in Fig. 6.4. In the waveforms, we can see that a clock pulse is generated at the end of the count (see ‘complete_tick’) i.e. ‘111’ in the current example.

Fig. 6.4 Simulation waveforms of N-bit binary counter, Listing 6.3

### 6.3.2. Mod-m counter¶

Mod-m counter counts the values from 0 to (m-1), which is designed in Listing 6.4.

Explanation Listing 6.4

The listing is same as Listing 6.3 with some minor changes which are explained here. In Line 5, maximum count i.e. M is defined for ‘Mod-m counter, then in Line 6, number for bits ‘N’ is defined which is required to count upto (M-1).

In Line 27, count is set to zero, when maximum count is reached otherwise it is increased by 1. Line 30 generates a tick for each count completion. The design generated by the listing is shown in Fig. 6.5.

Listing 6.4 Mod-m counter
  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 // modMCounter.v module modMCounter #( parameter M = 5, // count from 0 to M-1 N = 3 // N bits required to count upto M i.e. 2**N >= M ) ( input wire clk, reset, output wire complete_tick, output wire[N-1:0] count ); reg[N-1:0] count_reg; wire[N-1:0] count_next; always @(posedge clk, posedge reset) begin if (reset == 1) count_reg <= 0; else count_reg <= count_next; end // set count_next to 0 when maximum count is reached i.e. (M-1) // otherwise increase the count assign count_next = (count_reg == M-1) ? 0 : count_reg + 1 ; //Generate 'tick' on each maximum count assign complete_tick = (count_reg == M-1) ? 1 : 0; assign count = count_reg; // assign count to output port endmodule 

Explanation Fig. 6.5

This figure is same as Fig. 6.3 with few changes to stop the count at ‘M’. Firstly, in ‘Equal0’ component ‘32’h0…04’ (i.e. ‘M-1’) is used instead of 32’h0…07, as ‘M’ is set to 5 in Line 5; and the output of ‘Equal0’ is set to 1 whenever the count reaches to 4. Then output of ‘Equal0’ is sent to the multiplexer ‘MUX21’; which selects the count 3’h0 whenever the output of ‘Equal0’ is one, otherwise incremented value (given by ‘Add0’) is sent to the D flip flops. The simulation waveforms for this design is shown in Fig. 6.6. In the waveforms, we can see that a clock pulse is generated at the end of the count i.e. ‘100’ (see ‘complete_tick) in the current example.

Fig. 6.5 Mod-m counter, Listing 6.4

Fig. 6.6 Simulation waveforms of Mod-m counter, Listing 6.4

## 6.4. Clock ticks¶

In Listing 6.5, Mod-m counter is used to generate the clock ticks of different frequencies, which can be used for operating the devices which work on different clock frequencies. Further, we will use the listing for visual verification of the designs using ‘LEDs’ and ‘seven segment displays’.

Explanation Listing 6.5

The listing uses the ‘Mod-m’ counter (as shown Lines 19-23) to generate the ticks with different time period. In Line 8, M = 5 is set, to generate the ticks after every 5 clock cycles as shown in Fig. 6.8. In the figure, two ‘red cursors’ are used to display the 5 clocks cycles, and during $$5^{th}$$ cycle the output port i.e. ‘clkPulse’ is set to 1. Further, Fig. 6.7 shows the structure of the design, whose internal design is defined by Mod-m counter in Listing 6.4. Lastly, different values of ‘M’ and corresponding ‘N’ are shown in Lines 4-6, to generated the clock ticks of different time periods.

Listing 6.5 Generate clocks of different frequencies
  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 // clockTick.v module clockTick // M = 5000000, N = 23 for 0.1 s // M = 50000000, N = 26 for 1 s // M = 500000000, N = 29 for 10 s #( parameter M = 5, // generate ticks after M clock cycle N = 3 // N bits required to count upto M i.e. 2**N >= M ) ( input wire clk, reset, output wire clkPulse ); modMCounter #(.M(M), .N(N)) clockPulse5cycle ( .clk(clk), .reset(reset), .complete_tick(clkPulse) ); endmodule 

Fig. 6.7 Clock tick generator, Listing 6.5

Fig. 6.8 Simulation waveforms of clock tick generator, Listing 6.5

## 6.5. Seven segment display¶

In this section, Verilog code for displaying the count on seven segment display device is presented, which converts the hexadecimal number format (i.e. 0 to F) into 7-segment display format. Further, a test circuit is designed to check the output of the design on the FPGA board.

### 6.5.1. Implementation¶

Listing 6.6 is designed for active-low seven segment display device, i.e. LEDs of the device will glow if input is ‘0’. Then, at the end of the design, output is generated for both active low and active high seven segment display devices.

Fig. 6.9 Seven segment display

Explanation Listing 6.6

In the listing, hexadecimal number i.e. ‘hexNumber’ is converted into seven segment format i.e. ‘sevenSegment’. Lines 13 to 30 perform this conversion e.g. if hexadecimal number is 0 (i.e. “0000” in binary format), then it is converted into “0000001” in Line 14. Since, seven segment display device in the Altera DE2 board is active low, therefore ‘1’ is used in the end (i.e. ‘$$g^{th}$$’ position is set to ‘1’ in Fig. 6.9), so that $$7^{th}$$ LED will not glow and ‘0’ will be displayed on the seven segment display.

Since the design is for active low system, therefore in Line 33, the signal ‘sevenSegment’ is assigned directly to the output port ‘sevenSegmentActiveLow’; whereas it is inverted for the active high output port i.e. ‘sevenSegmentActiveHigh’ in Line 34. In this way, we can use this design for any kind of devices. In the next section, test circuit is shown for this design.

Listing 6.6 Hexadecimal to seven segment display conversion
  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 // hexToSevenSegment.v module hexToSevenSegment ( input wire[3:0] hexNumber, output wire[6:0] sevenSegmentActiveLow, sevenSegmentActiveHigh ); reg[6:0] sevenSegment; always @* begin case(hexNumber) 4'b0000 : sevenSegment = 7'b1000000; // 0 4'b0001 : sevenSegment = 7'b1111001; // 1 4'b0010 : sevenSegment = 7'b0100100; // 2 4'b0011 : sevenSegment = 7'b0110000; // 3 4'b0100 : sevenSegment = 7'b0011001; // 4 4'b0101 : sevenSegment = 7'b0010010; // 5 4'b0110 : sevenSegment = 7'b0000010; // 6 4'b0111 : sevenSegment = 7'b1111000; // 7 4'b1000 : sevenSegment = 7'b0000000; // 8 4'b1001 : sevenSegment = 7'b0010000; // 9 4'b1010 : sevenSegment = 7'b0001000; // a 4'b1011 : sevenSegment = 7'b0000011; // b 4'b1100 : sevenSegment = 7'b1000110; // c 4'b1101 : sevenSegment = 7'b0100001; // d 4'b1110 : sevenSegment = 7'b0000110; // e default : sevenSegment = 7'b0001110; // f endcase; end assign sevenSegmentActiveLow = sevenSegment; assign sevenSegmentActiveHigh = ~sevenSegment; endmodule 

### 6.5.2. Test design for 7 segment display¶

Till now, we checked the outputs of the circuits using simulation. In this section, output of the code is displayed on the Seven segment devices which is available on the DE2 FPGA board. Further, we can use the design with other boards as well; for this purpose, the only change required is the pin-assignments, which are board specific.

Verilog code for testing the design is presented in Listing 6.6. Note that, in this listing, we use the names ‘SW’ and ‘HEX0’ etc., which are defined in ‘DE2_PinAssg_PythonDSP.csv’ file. Partial view of this file is shown in Fig. 6.10, which is provided in the zip folder along with the codes and can be downloaded from the website. This file is used for ‘pin assignment’ in Altera DE2 board. DE2 board provides the 18 switches i.e. SW0 to SW17. Pin number for SW0 is ‘PIN_N25’, therefore in the ‘.csv file’, we used the name SW[0] for (SW0) and assign the pin number ‘PIN_N25’ in location column. Note that, we can not change the header names i.e. ‘To’ and ‘Location’ for using the ‘.csv file’. Further, we can change the names to any other desired names e.g. SW17 is named as ‘reset’, which will be used for resetting the system in later designs.

For pin assignments with ‘.csv file’, go to Assignments–>Import Assignments and then select the file ‘DE2_PinAssg_PythonDSP.csv’. Next, to see the pin assignments, go to Assignments–>Pin Planner, which will display the pin assignments as shown in Fig. 6.11. Further, we can manually change the pin location by clicking on the ‘Location’ column in the figure.

Note

Names ‘SW’ and ‘HEX0’ etc. are used along with ‘std_logic_vector’ in the testing circuits, so that pin numbers are automatically assigned to these ports according to ‘.csv file’. Otherwise we need to manually assign the pin numbers to the ports.

Fig. 6.10 Partial display of ‘Pin assignments file’ i.e. DE2_PinAssg_PythonDSP.csv

Fig. 6.11 Partial display of Pin Assignments

Explanation Listing 6.7

In Line 6 of the listing, 4 bit input port ‘SW’ is defined. Therefore, pin number will be assigned to these switches according to name ‘SW[0]’ to ‘SW[3]’ etc. in the ‘.csv file’. In Line 7, two output ports are defined i.e. HEX0 and HEX1. Next, in Line 10 and 13, HEX0 and HEX1 are mapped to active low and active high outputs of the Listing 6.6 respectively. Note that, it is optional to define all the output ports in the port mapping, e.g. output port ‘sevenSegmentActiveHigh’ is not declared in Line 11; whereas all the input ports must be declared in port mapping.

Now this design can be loaded on the FPGA board. Then, change the switch patterns to see the outputs on the seven segment display devices. Since, HEX0 and HEX1 are set for active low and active high respectively, therefore HEX1 will display the LEDs which are not glowing on the HEX0 e.g. when HEX0 displays the number ‘8’, then HEX1 will not glow any LED as all the LEDs of HEX0 are in the ‘on’ condition.

Listing 6.7 Test design for seven segment display
  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 // hexToSevenSegment_testCircuit // testing circuit for hexToSevenSegment.vhd module hexToSevenSegment_testCircuit ( input wire[3:0] SW, output wire[6:0] HEX0, HEX1 ); hexToSevenSegment hexToSevenSegment0 ( .hexNumber(SW), .sevenSegmentActiveLow(HEX0)); hexToSevenSegment hexToSevenSegment1 ( .hexNumber(SW), .sevenSegmentActiveHigh(HEX1)); endmodule 

## 6.6. Visual verification of Mod-m counter¶

In previous section, we displayed the outputs on 7 segment display devices, but clocks are not used in the system. In this section, we will verify the designs with clocks, by visualizing the outputs on LEDs and seven segment displays. Since, 50 MHz clock is too fast to visualize the change in the output with eyes, therefore Listing 6.8 uses the 1 Hz clock frequency for mod-m counter, so that we can see the changes in the outputs.

Explanation Listing 6.8

Since, DE2 provides clock with 50 MHz frequency, therefore it should count upto $$5 \times 10^7$$ to elapse 1 sec time i.e. $$\frac{{50MHz}}{{5 \times {{10}^7}}} = \frac{{50 \times {{10}^6}Hz}}{{5 \times {{10}^7}}} = 1Hz = 1\sec$$ . Therefore M=50000000 is used in Line 20.

In the listing, three component are instantiated i.e. ‘clockGenerator’, ‘modMCounter’ and ‘hexToSevenSegment’ for the visual verification of mod-m counter. Further, counts are verified using both LEDs and seven segment display. In Line 20, ‘clockGenerator’ is instantiated which generates the clock of 1 second i.e. ‘clk_Pulse1s’. Then this 1 second clock is used by second instantiation i.e. mod-m counter as shown in Line 27. This can be seen in Fig. 6.12 where output of ‘clockGenerator’ is connect with input clock of mod-m counter. Lastly, all these signals are sent to output port i.e. 1 second clock is displayed by LEDR[0] (Line 24), whereas ‘completed-count-tick’ is displayed by LEDR[1] (Line 29). Also, counts are displayed by green LEDs i.e. LEDG (Line 31). Further, seven segment display is also instantiated at Line 34, to display the count on seven segment display as well.

Listing 6.8 Mod-m counter verification with 1 second clock
  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 // modMCounter_VisualTest.v module modMCounter_VisualTest #(parameter M = 12, // count from 0 to M-1 N = 4 // N bits required to count upto M i.e. 2**N >= M ) ( input wire CLOCK_50, reset, output wire[6:0] HEX0, output wire [1:0] LEDR, output wire[N-1:0] LEDG ); wire clk_Pulse1s; wire[N-1:0] count; // clock 1 s clockTick #(.M(50000000), .N(26)) clock_1s (.clk(CLOCK_50), .reset(reset), .clkPulse(clk_Pulse1s)); assign LEDR[0] = clk_Pulse1s; // display clock pulse of 1 s // modMCounter with 1 sec clock pulse modMCounter #(.M(M), .N(N)) modMCounter1s (.clk(clk_Pulse1s), .reset(reset), .complete_tick(LEDR[1]), .count(count)); assign LEDG = count; // display count on green LEDs // display count on seven segment hexToSevenSegment hexToSevenSegment0 ( .hexNumber(count), .sevenSegmentActiveLow(HEX0)); endmodule 

Fig. 6.12 Mod-m counter verification with 1 second clock

## 6.7. Conclusion¶

In this chapter, we designed the circuit which generates various ‘ticks’ of different frequencies. Then the ticks are used for visual verifications of the designs using LEDs and seven segment displays. Further, structural modeling approach is used for the visual verifications of the systems.